Design of Signal De-DC System Based on FPGA

When using FPGA for digital signal processing, the DC component of the signal usually needs to be removed, and the DC component exists in the front stage of AD. If the analog circuit is used to remove the DC component, it is usually complicated to remove the DC component in the AD back-end digital domain. In the FPGA, the conventional method of going to DC is to accumulate the signal first, and then shift the accumulated value to obtain the DC component. For example, if the accumulated data is 8192, the DC component can be obtained by shifting the accumulated value to the right by 13 bits.

This paper introduces a de-dc module based on DSP48E1 resource design in Xilinx FPGA. The basic principle is to use first-order filter. As shown in Figure 1, through a first-order RC circuit, it can be equivalent to a low-pass filter at V0. A DC component is obtained.

figure 1

It can be deduced from the above formula that the coefficient is defined, and the following formula can be obtained:

From the above formula, the structure shown in Figure 2 can be obtained:

figure 2

Careful observation shows that the structure in Figure 2 is very similar to the DSP48E1 structure of Xilinx FPGA. As shown in Figure 3, the two structures are analogous. The subtraction of Vi - Vo can be realized by Pre-Adder in DSP48E1, k*(vi - vo The multiplication can be implemented by MulTIpler in DSP48E1, and the Vo + k*(vi - vo) addition can be implemented by Accumulator in DSP48E1. Therefore, only one DSP48E1 resource is needed to implement this DC module, and in Xilinx 7 series FPGA, DSP48E1 supports 25-bit Pre-adder, 25*18-bit MulTIpler and 48-bit Accumulator, which can basically meet the routine. deal with.

image 3

Implementation:

The macro definition of DSP48 can be found in the HDL language template of ISE. Here you need to use ADDMACC_MACRO. You only need to copy this macro template into the program to instantiate and call DSP48. The DSP48E1 implementation code of the DC module is as follows:

Module DCOff_DSP(

Input clk,

Input rst,

Input [15:0] din,

Output [15:0] dc

);

Wire signed [31:0] PRODUCT;

Wire signed [15:0] K;

Wire signed [31:0] ACOUT;

Assign K=16'h0085;

ADDMACC_MACRO #(

.DEVICE("7SERIES"), // Target Device: "VIRTEX6", "SPARTAN6", "7SERIES"

.LATENCY(4), // Desired clock cycle latency, 0-4

.WIDTH_PREADD(16), // Pre-adder input width, 1-25

.WIDTH_MULTIPLIER(16), // MulTIplier input width, 1-18

.WIDTH_PRODUCT(32) // MACC output width, 1-48

) ADDMACC_MACRO_inst (

.PRODUCT(PRODUCT), // MACC result output, width defined by WIDTH_PRODUCT parameter

.CARRYIN(1'b0), // 1-bit carry-in input

.CLK(clk), // 1-bit clock input

.CE(1'b1), // 1-bit clock enable input

.LOAD(1'b1), // 1-bit accumulator load input

.LOAD_DATA(PRODUCT), // Accumulator load data input, width defined by WIDTH_PRODUCT parameter

.MULTIPLIER(K), // Multiplier data input, width defined by WIDTH_MULTIPLIER parameter

.PREADD2(-PRODUCT[31:16]), // Preadder data input, width defined by WIDTH_PREADD parameter

.PREADD1(din), // Preadder data input, width defined by WIDTH_PREADD parameter

.RST(rst) // 1-bit active high synchronous reset

);

Assign dc=PRODUCT[31:16];

Endmodule