Circuit Design of High Speed ​​Data Acquisition System Based on AD9650

Overview:
A radar system operating in a high clutter environment requires a large instantaneous dynamic range to enable the acquisition of weak target signals. It is urgent to design a high-speed data acquisition system that achieves high dynamic range. In view of this, this paper studies the influence of ADC chip selection, clock design and front-end circuit design on the dynamic range of data acquisition system, and proposes a design scheme of high-speed data acquisition system based on AD9650. It is demonstrated that the design achieves a 16 b, 65 MSPS high-speed data acquisition system for collecting radar echo signals in high clutter environments.

0 Introduction With the development of digital signal processing technology, more and more signal processing links can be completed through the software processing of the back end, but this makes the requirements of electronic equipment for the front-end data acquisition system continue to increase. Because the processing effect of the back-end software depends on the amount of information contained in the data, only the dynamic performance of the data collection can improve the effect of the back-end processing. For a long time, in the field of data acquisition, the design and implementation of high-speed large dynamic range ADC system has always been a research hotspot. When the radar is working in a high-clutter electromagnetic environment, and the RCS or Doppler information of the detected object is very weak, an urgent need is put forward for designing a high-speed large dynamic range data acquisition system.
At present, the domestic design of high-speed large dynamic range ADC data acquisition system mainly depends on the chip's indicators and lacks systematic research and summary. This design aims to achieve a high-speed large dynamic range data acquisition system by optimizing the system design and combining the analog-to-digital conversion chip with superior dynamic performance.

1 System performance indicators require the main functions to be completed by the system: radar synchronization control; IF data acquisition, digital quadrature demodulation; signal preprocessing. At the same time, in order to reduce the power consumption of portable devices, the preprocessor is intended to use a low power processor. Due to the large dynamic range required, the IF acquisition requires high-precision data acquisition chips. It is designed as two channels. The required single-channel quantization digit is not less than 14 b, the effective digit is not less than 12 b, and the input signal range is 2 Vp-p. And meet the low power requirements.
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