Experts answer mixed-signal PCB design issues

1. In the system where digital and analog coexist, I have seen two kinds of processing methods. One is to separate the digital ground from the analog ground. For example, in the ground layer, the digital ground is an independent piece, and the simulation is independent. The single point is copper. The skin or FB beads are connected, and the power supply is not separated; the other is that the analog power supply and the digital power supply are connected separately by FB, and the ground is uniformly. Is the effect of these two methods the same?

A: It should be said that the principle is the same. Because the power supply and ground are equivalent to high frequency signals. The purpose of distinguishing the analog and digital parts is to prevent interference, mainly the interference of digital circuits to analog circuits. However, the segmentation may cause the signal return path to be incomplete, affecting the signal quality of the digital signal and affecting the EMC quality of the system. Therefore, no matter which plane is divided, it depends on whether the signal return path is increased and how much the recirculation signal interferes with the normal working signal. There are also some hybrid designs, regardless of the power supply and ground. In the layout, the layout is separated according to the digital part and the analog part to avoid cross-region signals.

2. The CMOS drive signals of multiple analog multiplexers and analog switches in the layout area of ​​the multi-channel 12_bit CCD analog video signal sampling circuit in my PCB design must be separated by digital analog under multiple ADCs (in different locations) Several 0 ohm resistors are shorted to the digital analog ground. The signal termination method at this time: the foreign model uses the source terminal 120R, and the load terminal uses a 5K resistor to terminate the ground with 2 or 4 TTL compatible COMS loads. These lines are 6 mils wide and 4 inches long. The distance between the copper layers is about 5-8 mils. Does this have a discrepancy with the 120 ohm source matching impedance, and whether the presence of a 5K resistor will also cause an increase in the drive current, increasing the interference of the digital to the analog portion, if the distance between multiple receivers is as long as 0.8 inch, this 5K resistor How to adjust the position, or need to change the matching method. If the above matching method is correct, how should it be calculated and how to treat the split wiring that violates the design rules.

Answer: For cross-segmented signals, it is better to use a 0 ohm resistor to short the digital analog ground than to use a parallel ground wire clamp or use a bypass capacitor. It is rare to use a 120 ohm series resistor at the source end. Is this drive signal a voltage-driven digital signal? Is there a power requirement for this termination? If it is a voltage-efficient digital signal, then simulation model simulation is required. Estimate the location and size of the match.

3. In modern high-speed PCB design, in order to ensure signal integrity, it is often necessary to terminate the input or output of the device. What are the methods of termination? What factors are used to determine the termination method? What are the rules? I hope the experts can give detailed answers or tell me where to find information to solve these problems.

A: Terminal, also known as matching. The active end matching and the terminal matching are generally classified according to the matching position. The source-side matching is generally resistance series matching, and the terminal matching is generally parallel matching. There are many ways, such as resistance pull-up, resistance pull-down, Dyvenan matching, AC matching, and Schottky diode matching. The matching mode is generally determined by the BUFFER characteristics, the topology, the type of the level, and the decision mode. The duty cycle of the signal and the power consumption of the system are also considered. The most critical aspect of digital circuits is the timing problem. The purpose of the matching is to improve the signal quality and obtain a determinable signal at the decision time. For the level effective signal, the signal quality is stable under the premise of ensuring the establishment and holding time; for the delay effective signal, the signal change delay speed meets the requirements under the premise of ensuring the signal delay monotonicity. Some information about matching is available in the Mentor ICX product textbook. In addition, "High Speed ​​Digital design a hand book of blackmagic" has a chapter dedicated to the terminal, from the principle of electromagnetic waves to describe the effect of matching on signal integrity, I believe that after reading, the understanding of matching will be more thorough.

4. In today's wireless communication equipment, the radio frequency part often adopts a miniaturized outdoor unit structure, so the volume structure is greatly limited, and thus the radio frequency part, the intermediate frequency part of the outdoor unit, and even the low frequency circuit part for monitoring the outdoor unit are often It is deployed on the same PCB. What are the requirements on the material of such a PCB? How to prevent interference between RF, IF and even low-frequency circuits? Mentor has no solution in this regard.

A: Hybrid circuit design is a big problem. It's hard to have a perfect solution. Generally, the RF circuit is laid out as a separate single board in the system, and even a special shielding cavity is provided. Moreover, the RF circuit is generally single-sided or double-sided, and the circuit is relatively simple, all of which are designed to reduce the influence on the distribution parameters of the RF circuit and improve the consistency of the RF system. Compared with the general FR4 material, the RF circuit board tends to be a substrate with a high Q value. The dielectric constant of this material is relatively small, the transmission line distribution capacitance is small, the impedance is high, and the signal transmission delay is small. In the hybrid circuit design, although the radio frequency and digital circuits are on the same PCB, they are generally divided into a radio frequency circuit area and a digital circuit area, and are respectively arranged and routed. Shielded between grounded vias and shielded boxes. Mentor's board-level system design software, in addition to basic circuit design features, also has a dedicated RF design module. In the RF schematic design module, a parameterized device model is provided, and a bidirectional interface with an RF circuit analysis simulation tool such as EESOFT is provided; in the RF LAYOUT module, a pattern editing function dedicated to the layout of the RF circuit is provided, and The bidirectional interface of the RF circuit analysis simulation tool such as EESOFT can reverse the schematic and PCB for the analysis and simulation results. At the same time, using the design management function of Mentor software, design reuse, design derivation, and collaborative design can be easily realized. Greatly accelerate the hybrid circuit design process. The mobile phone board is a typical hybrid circuit design, and many large mobile phone design manufacturers use Mentor plus Angeline's eesoft as the design platform.

5. How to better avoid the impact of high frequency part on the system? For example, 206M CPU, 100M or more SDRAM, etc. How to deal with the layout and wiring to ensure the stability of signals above 50M?

A: The key to high-speed digital signal routing is to reduce the impact of the transmission line on signal quality. Therefore, the high-speed signal layout above 100M requires the signal trace to be as short as possible. In digital circuits, high-speed signals are defined by the signal rise time. Moreover, different types of signals (such as TTL, GTL, LVTTL), the method of ensuring signal quality is different.

6, there is a question to ask, on a 12-layer PCb board, there are three power layers 2.2v, 3.3v, 5v, the three power supplies are made in one layer, no problem, how to deal with the ground line, is with the power supply In one correspondence, one layer is still used, and the other two ground layers are only used as structural layers.

A: Generally speaking, the three power supplies are respectively in the third layer, which is better for signal quality. Because it is unlikely that the signal will split across the plane layer. Cross-segmentation is a key factor affecting signal quality, and simulation software generally ignores it. For power and ground layers, it is equivalent for high frequency signals. In practice, in addition to considering the signal quality, power plane coupling (using adjacent ground planes to reduce the power plane AC impedance), stack symmetry, are all factors to consider.

7. For a full digital signal PCB, there is an 80MHz clock source on the board. In addition to the use of wire mesh (grounding), in order to ensure sufficient driving capability, what kind of circuit should be used for protection. In addition, if a separate clock signal board is used, what kind of interface is generally used to ensure that the transmission of the clock signal is less affected.

Answer: 1. What is the screen (grounding)? Is it grid copper? 2, to ensure the driving ability of the clock, should not be achieved through protection, generally using a clock driver chip. The general concern about clock drive capability is due to multiple clock loads. Using a clock driver chip, a clock signal is turned into several, using a point-to-point connection. Select the driver chip, in addition to ensuring a basic match with the load, the signal edge meets the requirements (generally the clock is along the valid signal). When calculating the system timing, it is necessary to count the clock delay in the driver chip. 3. The shorter the clock signal, the smaller the transmission line effect. Using a separate clock signal board increases the signal routing length. Moreover, the grounding power supply of the board is also a problem. For long distance transmission, a differential signal is recommended. The LVDS signal can meet the drive capability requirements, but your clock is not too fast and is not necessary.

8, the same chip, there is a 2.8V digital power input, there is a 2.8V analog power. Can you connect the two through an inductor and share an LDO. Just like digital ground and analog ground. Another: What is the 0 ohm resistor used for, can it be interchanged with the inductor?

A: Under normal circumstances, it is possible to share LDO. The classic one is pi filter (not directly connected by inductor); but if the chip itself has high requirements on the isolation of digital and analog power supplies, so that PI filtering cannot meet the requirements, then respectively Powered by different LDOs. 0ohm resistors are generally used for redundancy or optional design. They are similar to the function of jumpers. If they are not considered parasitic, they are not inductive and cannot be filtered. Therefore, they cannot be interchanged with inductors.

9. I want to know the industry's process of design verification for analog-to-digital mixed signals. As far as I understand, design verification plays a decisive role in the design process and directly affects the final success or failure of the chip. Design verification is divided into different levels, such as system level verification, circuit block level verification, analog-to-digital hybrid simulation, and final physical verification or post-simulation. How can design verification engineers ensure that the system verification is consistent with the final layout level verification? The reason for this is that the time and cost of different abstract level simulations are different. It can be said that the gap is huge, system level abstraction The level is relatively high, the system simulation can be completed in a short time, but to the verification of the layout level, there is almost no way to do the post-simulation of the entire chip. Without the post-simulation of the entire chip, the consistency between the system simulation and the final chip implementation cannot be effectively guaranteed. I don't know what the industry is more popular. What I want to know is a general process that goes away from using tools.

A: This is a very good question, very professional. As you said, the time cost of different abstract level simulations is different, and it is normal to have a time difference of even an order of magnitude. Because as the amount of data increases, the amount of computation for verification increases exponentially. Then, when it comes to post-chip simulation, especially for the whole chip, the amount of data of the parasitic RC parameters will increase a lot compared with the original device and the number of nodes. At this time, the amount of calculation is much more amazing, even if there are good hardware facilities. Support, a verification run for a few months or even longer is very common. At this time, in order to solve this problem, the usual practice is this: 1, using the fast-spice level simulator instead of the spice level simulator, That is to sacrifice a little precision for more capacity and speed; 2, let Digital's module become a real Digital. In the early digital-analog hybrid overall verification, because of the limitations of the verification tool, the digital circuit's gate-level is often Also run as a translator-level. This has the advantage of a simple process and a single tool. But the disadvantages are obvious. The amount of calculation is increased, and more calculations are placed on the part of the digital circuit that is not needed. (Because the digital-analog hybrid circuit tends to have more digital parts than the analog part) Even if the accuracy of some digital circuit parts can be lowered, it is a great waste of resources. The current trend is that when extracting the layout, the digital portion is still a gate-level, using a true digital-analog mixed-signal simulator for simulation. 3. Abstract the simulation part into a high-level AMS. This greatly improves the verification efficiency. In fact, many IPs also use AMS for overall verification.

10. I want to use an analog circuit to solve a 4th order differential equation for real-time control, which is faster. Specifically, the signal to be integrated calculated by the MCU is introduced into the analog integrator through D/A, and the result of the integration is sent back to the MCU through A/D for control. I wonder if this is feasible, mainly considering accuracy and interference. If it is feasible, can you recommend an integrating chip, or do I take the integration circuit myself? If the whole system includes an adder, is the multiplier designed to simulate the chip is not feasible, what should I pay attention to?

A: It seems to be feasible. Maybe you can try the program first with MATLAB. Because I don't know the details, I can't recommend specific practices for you. You can search online to see if there is any integrated chip that meets your specific requirements. If you have one, use the ready-made one. It is too much trouble to take the circuit yourself, and it cannot guarantee performance. In general, the adder multiplier is considered to be implemented by a digital circuit, and it is common to integrate it into a hybrid chip. Remind that these tasks are unlikely to be done by one person independently. If you want to verify the system's feasibility, you can consider running simulation with AMS first.

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