FPGA basics (1): Blocking and non-blocking assignments, not just one clock cycle worse than the original signal!

Blocking and non-blocking assignments

First of all, from the name, the blocking assignment is that the assignment is not completed, the latter statement will not be executed, and the non-blocking just happens to be the opposite, that is, the assignment is not completed and does not hinder the execution of subsequent programs, so we often say that the non-blocking assignment object is not Immediately get a new value, if you look at the timing, the assigned object will be one clock cycle worse than the assigned object.

With the above understanding, we can easily understand why the object that blocks the assignment changes immediately. In fpga, we are more exposed to the sequential circuit, and do not want to be changed immediately by the assigned object, so for the combined circuit, Commonly used blocking assignments, sequential circuits are often used for non-blocking assignments.

Let's look at an example that everyone is familiar with:

Look at the non-blocking code first:

Clk is the clock after the main clock is divided, clk is first assigned to a, then a is assigned to b, take a look at the generated circuit diagram

It can be seen that there are two triggers, and the output of the previous trigger is the input of the latter trigger, and then look at the blocking

Since there is no trigger generated for the combined circuit, the two differences are seen from the simulation results.

I believe that everyone can easily see which is blocked and which is non-blocking. From the non-blocking timing, a delays a master clock from clk, and b delays a master clock by a, which is not what I want to say. Focus, I want you to see when a and b start to change. The textbook always says that when the whole process ends, the values ​​of a and b are updated. Do you know when the process ends? From the simulation results, it is better to understand that the value of a, b changes immediately upon the rising edge of each clock, but only one clock cycle worse than the original signal.