Power Design Tip 41: DDR Memory Power (see PDF for full text!)

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The power consumption of a CMOS logic system is primarily related to the clock frequency, the input capacitance of each gate in the system, and the supply voltage. As the device size is reduced, the supply voltage is also reduced, resulting in significantly lower power dissipation at the gate layer. This low-voltage device has lower power consumption and higher operating speed, allowing the system clock frequency to rise to the gigahertz level. At these high clock frequencies, impedance control, proper bus termination, and minimal cross-coupling result in high fidelity clock signals. Traditionally, logic systems only clock data for one clock edge, while double data rate (DDR) memory clocks both the leading and falling edges of the clock. It doubles the speed of data throughput and increases system power consumption.

This article presents two alternative bus termination schemes. In the first scheme (A), the bus termination resistor is placed at the end of the distribution network and connected to ground. In the second option (B), the terminating resistor is connected to the supply voltage (VTT) and the supply voltage is half of the VDD voltage.

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