Cascaded PLL clock processor has minimal impact on system timing

With the rapid development of the communications market, the complex tree structure for clock distribution has been widely used. In order to feed signals to many nodes that are used by clock distribution and other designs to transmit data (combined units designed with many different functions with digital time domain accuracy), a clock tree is necessary. Since a large number of clocks need to be used to time multiple nodes in the system, it is imperative to generate these timing clocks within a strict, very accurate and limited window time.
Currently, these windows are measured in picoseconds. As the number of nodes to which signals must be fed increases and the timing window into which the clock must be placed is rapidly reduced, designers must understand the characteristics of the devices used to complete the generation, frequency multiplication, and transmission of these clock signals. Many of today's clock signal generation and transmission products include PLL, which further increases the complexity of the timing system. These PLLs enable designers to retime lagging or leading clocks, eliminate propagation delays that occur during long-distance clock signal transmission, and generate clock signals that are phase-locked to a reference clock and have different frequencies.
While using the PLL to obtain these clock control capabilities, it also brings degradation of the reliability of the PLL. It is necessary to understand the degradation of signal quality caused by all PLL-based clock processing components and provide a certain tolerance. The noise added by the PLL to the clock signal it processes cannot be completely eliminated. This noise is often tolerated. Moreover, the components in the clock tree that contain the PLL can be configured and controlled so that they are The noise generated is controlled and the total clock tree performance is much higher than the acceptable minimum.
The accumulation of noise imposed by the PLL on the clock signal transmitted or generated by it is jitter. In electrical terms, jitter refers to the time deviation of a specified clock point (usually the rising or falling edge of a pulse under a specified voltage condition) relative to its absolute expected point. This jitter has traditionally been divided into two categories. The first type is short-term jitter, which is measured based on the displacement of a point in time relative to its ideal position in adjacent clock cycles. The common term used for this parameter is period-to-period jitter.

Figure 1 Phase-locked loop (PLL)

Figure 2 Typical jitter transfer function curve of a zero-delay buffer

Another type of jitter is measured over a longer period of time. One term used for this type of jitter is long-term jitter. The term with higher frequency and accuracy is long-term period jitter. In this field, a length of time (in cycles or seconds) must be specified to limit the sampling period of events to generate measured values. If the sampling period is not limited, the event may drift in an uncertain position. Therefore, the measurement period for measuring the occurrence rate of the event must be set and explained in order to more accurately specify the specific measurement method. For a specific application, it is usually related to the stability that the pulse edge must have within a specific period.
In the process of building a clock tree with reasonable values, it is inevitable to connect clock processing components based on PLL in series. In this case, it is necessary to understand the mutual influence between the jitter caused by each component, and it is more important to understand the jitter content of all the final component clocks generated by the clock tree. This article will give a comprehensive discussion from the perspective of principle and function.
When engineers prepare to adopt a design that includes multiple serial PLL clock processing elements, they often face two sources of information. The first source of information is the traditional knowledge possessed by RF designers. Although there are many introductions based on RF PLL design, they often involve circuits that mix two PLL-based signals to generate a sum clock or a differential clock. Moreover, they generally do not have picosecond timing limitations like digital designs. There is a lot of theoretical information available in the field of digital clocks, but what the designer needs is some empirical information or evidence to transform the application problem into a clear and predictable point of view, that is, to clarify the design goals and should Where should the design time and resources be concentrated to achieve a sound design plan?
This article will study the performance obtained by a special and typical experiment using 5 series PLLs. Although we do not recommend that you adopt the design scheme of 5 PLL devices in series configuration, this scheme is deliberately adopted here to embody the various adverse effects that the designer cares about.
When studying PLL-based clock processing components, the first thing you need to understand is their role in the clock signals that must be passed through them. Figure 1 shows a typical ZDB (zero delay buffer) element and its components.
The most important thing for electrical performance is the series element group consisting of phase detector, error amplifier, charge pump and loop filter. For an input reference clock signal, these components act as a second-order low-pass filter. Figure 2 shows the jitter and frequency transfer functions and the bandwidth response of the device used in this example.
This is a graph of the input-output transfer function. It indicates the gain (and loss) of any input frequency to the component. Please note that the input frequency (either the frequency itself can also be loaded on the input reference signal) will pass through the loop filter and phase detector combined stage for transmission and amplification. Frequencies higher than the 1.5MHz roll-off point (and frequency components of complex waves) will be attenuated due to the filtering effect, and thus will be suppressed when passing through the device.
In order to analyze and explain the effect of the PLL clock processing device on the clock signal passed through it, the following will divide the noise that exists on the clock signal through several consecutive stages in three different views.
The first is the frequency domain view. This view will use a spectrum analyzer to observe the graph of the power level as a function of frequency to understand how this noise is propagated in the system.
The second is the long-period jitter view. Here you can observe how the output clock works over a long period of time, as well as the actual frequency distribution of these periodic changes. The measurement will use a TIA (Time Interval Analyzer) to show the relationship between the amount of occurrence (total) and frequency.
The third is the modulation domain view. In this view, you can observe the cycle-to-cycle (CC) or the frequency change between adjacent cycles in a series of medium-length cycles. It will show the presence of pulses or instantaneous frequencies (jitter) and a mid-range view.
The device used in this article has the following data sheet features:
·200ps CC jitter ·1MHz PLL loop bandwidth There is a fairly flat noise floor on both sides of the reference carrier frequency. The width and slope of the carrier frequency sweep trace depend on the video performance and resolution bandwidth settings of the spectrum analyzer. It is important to pay attention to the flatness of the noise floor relative to the rising and falling edges of the reference clock pulse, because we are concerned about the flatness changes between the processing stages.
It can be seen from Figure 2 and related explanations that the PLL-based clock device functions as a low-pass second-order filter in the frequency domain. In the process of studying the spectral content of each successive stage, it can be clearly found that the noise located in the passband of the loop filter is transmitted in successive stages and is amplified step by step. In fact, for the output of the second and subsequent stages, there is a definite peaking of the spectral energy transmitted through these. It corresponds to the slight peaking at the edge of the pass band shown in Figure 2. The second concern is the noise floor outside the passband of the device. Please note that even after 5 levels of gain, the noise floor is still close to the input signal (top and bottom) level of the waveform amplitude.
For frequencies close to the reference frequency, the PLL-based clock device does act as a low-pass filter. Low frequency (close to the carrier frequency) energy and signal components will easily pass through the device. This means that the low frequency energy (in terms of performance, it will be converted into a low frequency and the slow movement or drift of the output frequency) will be transmitted and amplified as the signal passes through the continuous processing stage. Who will control the final value (the deviation from the input reference to the first stage expressed in units of frequency) depends almost entirely on the bandwidth of the device and any other efforts to suppress it between the stages of the clock tree.
The second view we will study is the long-term or periodic jitter view.
The first thing to note is that the density distribution is essentially a Gaussian function. This supports the known fact that the random jitter caused by the actual noise inside the component or the inherent white noise in the input signal will appear on the signal as a highly predictable Gaussian distribution extension (frequency modulation) effect. The second thing to pay attention to is the impact of the noise on the total amplitude of the clock signal on multiple processing stages, and the accumulation and broadening of the noise as it passes through each additional processing stage (distributed in a wider frequency range).
It should be noted that these frequencies are close to the fundamental frequency. This is in line with the point of this article because it shows that noise and energy components close to the passband of the device (or within the passband of the device) are not transmitted only by the device that amplifies it. Similarly, since the noise (jitter) is close to the operating frequency of the device, the rate of occurrence of jitter is very slow. It is based on this fact that the overall effect is to make the second stage track the error of the first stage signal, the third stage tracks the error of the first and second stages, and the final stage tracks the accumulation of all processing stages before it ( Additive) error.
The high-frequency domain period to period jitter of the clock accumulates between stages, and its increment is very small. In some systems, it may even be reduced when passing through certain processing stages. The reason for this is that cycle-to-cycle jitter occurs between adjacent cycles of the clock. In this example, the base frequency of the clock is 106.25MHz. In order for the waveform to respond to an impulsive noise (short-term and high-frequency parts of the frequency content of the spectrum), its frequency will have to be above 100 MHz. Otherwise, the influence of noise will be spread over many cycles. Due to the narrow loop bandwidth of the device, this type of energy is filtered through the edge of the bandpass curve, and therefore it is not easy to propagate between levels. In a precisely designed system, wide-bandwidth components can be used to deliver such man-made modulation interference as the required EMI suppression with spread-spectrum modulation signals (at a cycle rate lower than 35kHz). Therefore, in order to reduce the accumulated high-frequency jitter of the system, a very narrow bandwidth PLL device can be used to effectively filter this and other high-frequency noise before applying the target system equipment.
Summarize what this example illustrates. First, when the signal passes through a continuous PLL-based clock processing stage, the low-frequency noise contained within the bandpass characteristics of the PLL-based device will propagate and be amplified and accumulated. If the system being designed is a time base (clock) that requires long-term stability and is not adversely affected by the instantaneous turn-off frequency, the method of connecting PLL clock processing devices in series will have the least impact on the system. Due to the long-term Gaussian balancing process, any short-period changes will eventually be balanced.
Therefore, if two to three consecutive clocks are used to very tightly time events in the system, this is not a problem, because the accumulation time of the long period jitter is too long, so it is impossible to form sufficient time for adjacent clock cycles. The error that has an impact on the occurrence of the event. In these applications, it is common practice to time the dynamic memory, CPU, and other devices that exchange data with them. Here, although the stability of three consecutive clocks in a RAS-CAS-READ cycle has a vital impact on the instant, long-cycle changes over a 1000 cycle span have almost no impact.
On the other side of the spectrum, it can be seen that very fast (far beyond the PLL bandwidth used by the device) jitter does not pass through a system with multiple PLL-based clock devices. The period-to-period jitter present at the output of any device is almost the same as the jitter to the device under test. This means that devices that are very sensitive to period/frequency changes in adjacent or very close periods of their clock pulses are expected to work well with series-connected, PLL-based clock device trees. The main negative impact on applications using PLL-based tandem clock device trees occurs in specific data applications, in which an input data stream has many consecutive data bits divided into very specific and dispersed time windows. In such applications, when restoring data from a data stream, a long-term shift of the clock generated by a long PLL-based component tree may cause the clock signal to fall outside the desired unit time domain.