Deep interpretation of Σ-Δ ADC topology principle

The Σ-Δ ADC is an essential component in the toolbox of today's signal acquisition and processing system designers. The purpose of this article is to give the reader a basic understanding of the fundamentals behind the Σ-Δ model ADC topology. This article explores a trade-off analysis example of noise, bandwidth, settling time, and all other key parameters associated with ADC subsystem design.

It usually consists of two modules: a sigma-delta modulator and a digital signal processing module, which is usually a digital filter. A brief block diagram and main concepts of the Σ-Δ ADC are shown in Figure 1.

Figure 1. Key concepts of Σ-Δ ADC

The sigma-delta modulator is an oversampling architecture, so we begin with Nyquist sampling theory and schemes and oversampling ADC operation.

Figure 2 compares the Nyquist operation of the ADC, the oversampling scheme, and the sigma-delta modulation (also oversampling) scheme.

Figure 2a shows the quantization noise when the ADC is operating in the standard Nyquist mode. In this case, the quantization noise is determined by the LSB size of the ADC. FS is the sampling rate of the ADC and FS/2 is the Nyquist frequency. Figure 2b shows the same converter, but now it runs in oversampling and the sampling rate is faster. The sampling rate is increased by a factor of K, and the quantization noise is extended to the bandwidth of K & TImes; FS/2. A low-pass digital filter (usually with a decimation function) eliminates quantization noise outside of the blue region.

Figure 2a. Nyquist scheme. Sampling rate is FS, Nyquist

Bandwidth is FS /2

Figure 2b. Oversampling scheme. The sampling rate is K &TImes; FS

Figure 2c. Σ-Δ ADC scheme. Oversampling and noise shaping, sampling rate is FMOD = K &TImes; FODR

One additional feature of the sigma-delta modulator is noise shaping, as shown in Figure 2c. The analog-to-digital conversion quantization noise is modulated and shaped, moving from low frequencies to higher frequencies (usually), and the low-pass digital filter removes it from the conversion result. The noise floor of a Σ-Δ ADC is determined by thermal noise and is not limited by quantization noise.

The Σ-Δ ADC uses an internal or external sample clock. The ADC's main clock (MCLK) is often divided first and then used by the modulator; pay attention to this when reading the ADC data sheet and understand the modulator frequency. The clock transmitted to the modulator sets the sampling frequency FMOD. The modulator outputs data to the digital filter at this rate, and the digital filter (usually low pass with decimation) provides data at the output data rate (ODR). Figure 3 shows the process

Figure 3. Σ-Δ ADC flow: from modulator output to digital filtering

The sigma-delta modulator is a negative feedback system similar to a closed loop amplifier. The loop contains a low resolution ADC and DAC, as well as a loop filter. The output and feedback are roughly quantized, often with only one bit representing a high or low output. The ADC's analog system implements this basic structure, and the quantizer is the module that performs the sampling. If there is a condition that guarantees loop stability, then the output is a rough representation of the input. The digital filter obtains this coarse output and reconstructs the exact digital conversion result of the analog input.

Figure 4 shows a 1-density output in response to a sine wave input. The rate of change of the modulator output from low to high depends on the rate of change of the input. When the sine wave input is positive full scale, the modulator output switching rate is reduced and the output is dominated by the +1 state. Similarly, when the sine wave input is negative full scale, the transition between +1 and –1 is reduced and the output is dominated by –1. When the sine wave input is at the maximum rate of change, the modulator output produces the highest density of +1 and –1 switching. The output rate of change is synchronized with the input rate of change. Therefore, the analog input is described by the slew rate of the sigma-delta modulator output.

If a linear model is used to describe such a 1-bit modulator (Mod 1), the system can be represented as a control system with negative feedback. The quantization noise is the difference between the input and output of the quantizer. The input deviation node is followed by a low pass filter. In Figure 5b, the quantization noise is represented by N.

H(f) is a function of the loop filter that defines the transfer function of noise and signal. H(f) is a low-pass filter function that has a very high gain at low frequencies (within the target bandwidth) that attenuates high frequency signals. The loop filter can be implemented as a simple integrator or integrator cascade. In practice, a DAC is often placed in the feedback path to obtain a digital output signal and convert it to an analog signal that is fed back to the analog input bias node.

Figure 4. Density of the Σ-Δ output 1 code value of the input sine wave. Linear model of a 1st order Σ-Δ modulator loop (a)

Figure 5. Linear model of the Mod 1 Σ-Δ loop (b), including equations, filters, signals, and noise transfer function diagrams

The signal and noise transfer function can be obtained by solving the equation shown in Fig. 5. The signal transfer function acts as a low pass filter with a gain of 1 in the target bandwidth. The noise transfer function is a high-pass filter function that provides noise shaping and has a strong rejection of quantization noise at lower frequencies near DC. The quantization noise seen at higher frequencies outside the target bandwidth increases. For the first order modulator (Mod 1), the noise is increased at a rate of approximately 20 dB/decade.

To increase system resolution, a common approach is to cascade two loop filters to increase the loop filter order. Now, the total loop filter's H(f) has a larger roll-off, and the Mod 2 type noise transfer function has a 40 dB/decade octave rate. The lower the frequency at which the noise is located, the more the noise shaping becomes. Figure 6 compares Mod 1 and Mod 2 sigma-delta ADCs. The sigma-delta modulator has a lot of variations and styles. The architecture that circumvents the high-order 1-bit loop stability problem is called the multi-level noise shaping modulator (MASH) architecture. The multi-stage (MASH type) architecture supports the design of stable high-order sigma-delta modulators through low-order loop combinations with inherent stability.

Figure 6. Mod 1 and Mod 2 block diagram configuration and comparison of filter and noise transfer functions