What is the mips instruction set?

MIPS is the most elegant of the highly efficient Reduced Instruction Set Computer (RISC) architecture; even MIPS competitors believe that this can be derived from MIPS's later development of new architectures such as DEC's Alpha and HP's Precision. The strong influence is seen. While its elegant design does not guarantee long-lasting competition in a competitive market, MIPS microprocessors often keep the fastest in design at every stage of the processor's technology development.

The instruction set is a hard program stored inside the CPU that guides and optimizes CPU operations. With these instruction sets, the CPU can run more efficiently. The MIPS instruction set is a reduced instruction set. All instructions of MIPS are 32 bits, the instruction format is simple, and the instruction length of X86 is not fixed. Simple instructions and formats are easy to decode and pipeline, but the code density is not high, resulting in large binary files.

The low-end CPU has a physical area of ​​only 1.5 square millimeters (which is hard to find in the SOC system). The high-end R10000 processor, when it was first put on the market, may be the fastest CPU in the world. Its physical area is almost 1 square inch and its heat is nearly 30 watts. Although MIPS does not seem to have any advantages, it is sufficient for sales to grow healthily: the majority of the 44M MIPS CPUs that were launched in 1997 are used in embedded applications.

MIPS (Million InstrucTIons Per Second): The abbreviation of the average execution speed of single-point fixed-point instructions Million InstrucTIons Per Second, the number of machine-level instructions of millions of machines processed per second. This is an indicator of CPU speed. For example, an Intel80386 computer can process 3 to 5 million machine language instructions per second, that is, we can say that the 80386 is a 3 to 5 MIPS CPU. MIPS is only an indicator of CPU performance.

MIPS is a popular RISC processor in the world. MIPS means "Microprocessor without interlocked piped stages". The mechanism is to use software as much as possible to avoid data related problems in the pipeline. It was first developed in the early 1980s by a research team led by Professor Hennessy of Stanford University. MIPS' R series is a microprocessor for RISC industrial products developed on this basis. These series of products are used by many computer companies to form a variety of workstations and computer systems.

MIPS Technologies is a well-known chip design company in the United States that designs chips using the Reduced Instruction System Computing Architecture (RISC). Compared with the complex instruction system computing architecture (CISC) adopted by Intel, RISC has the advantages of simpler design and shorter design cycle, and can apply more advanced technologies to develop faster next-generation processors. MIPS is one of the earliest commercial RISC architecture chips. The new architecture integrates all of the original MIPS instruction sets and adds many more powerful features.

1, R (register) type of instruction. This type of instruction reads two source operands from the register file and writes the result back to the register file.

2. I (immediate) type of instruction. This type of instruction uses a 16-bit immediate value as a source operand.

3. J (jump) type of instruction. This type of instruction uses a 26-bit immediate value as the target address for the jump.

1, arithmetic operations.

2. Logical operations.

3. Data transfer.

4. Conditional transfer.

5. Unconditional jump.

6, special instructions.

7. Exceptional instructions.

8, coprocessor instructions.

9. The system controls the coprocessor instructions.

The MIPS processor is a hot spot in the design of RISC CPUs in the mid-1980s. MIPS is the best RISC CPU sold, and can be seen from anywhere, such as Sony, Nintendo consoles, Cisco routers and SGI supercomputers. At present, with the RISC architecture being dominated by x86 chips, MIPS may be the only one in the original RISC CPU design to be profitable in this century. Compared with Intel, MIPS license fees are relatively low, which is used by most chip manufacturers except Intel.

MIPS' system structure and design concept are relatively advanced. Its instruction system has passed the general processor instruction system MIPS I, MIPS II, MIPS III, MIPS IV to MIPS V. The development of embedded instruction system MIPS16, MIPS32 to MIPS64 is very mature. In terms of design concept, MIPS emphasizes hardware and software synergy to improve performance while simplifying hardware design.

China's Loongson 2 and its predecessors use 64-bit MIPS instruction architecture, which is incompatible with the commonly known X86 instruction architecture. The MIPS instruction architecture was created by MIPS and belongs to the RISC system. In the past, MIPS architecture products were more common in the workstation field. The "EmoTIon Engine" used in Sony PS2 game consoles also adopted the MIPS command. The performance of these MIPS processors is very strong, and Loongson 2 also belongs to this camp, in terms of software and the above products. Fully compatible.

Lb/lh/lw: Reads a byte/half word/word data from the memory into the register. Such as lb $1, 0 ($2)

Sb/sh/sw: Stores a byte/half word/word data from a register into memory. Such as sb $1, 0 ($2)

Add/addu: Adds the contents of the two fixed-point registers add $1, $2, $3 ($1=$2+$3); u is unsigned plus.

Addi/addiu: Add the contents of a register to an immediate add $1, $2, #3 ($1=$2+3); u is unsigned.

Sub/subu: Subtracts the contents of two fixed-point registers.

Div/divu: Divide the contents of the two fixed-point registers.

Mul/mulu: Multiplies the contents of the two fixed-point registers.

And/andi: AND operation, the contents of the two registers are combined with and $1, $2, $3 ($1=$2 & $3); i is an immediate value.

Or/ori: or operation.

Xor/xori: XOR operation.

Beq/beqz/benz/bne: conditional transfer eq is equal, z zero, ne not equal.

j/jr/jal/jalr: ​​j direct jump; jr uses register jump;

Lui: Fill a 16-bit immediate value into the upper 16 bits of the register and the lower 16 bits to fill the zero.

Sll/srl: logically shifted left/right by sll $1, $2, #2.

Slt/slTI/sltui: If the value of $2 is less than $3, set the value of $1 to 1, otherwise set the value of $1 to 0. Slt $1, $2, $3.

Mov/movz/movn: copy, n is negative, z is zero. Mov $1, $2; movz $1, $2, $3 ($3 is zero to copy $2 to $1).

Trap: Goes to the pipe state according to the address vector.

Eret: Return from the exception to the user mode.

32 general purpose registers

0 ($zero): always returns a value of 0

1 ($at): used as a temporary variable of the assembler

2-3($v0-$v1): Subfunction call returns result

4-7($a0-$a3): Parameters of the subfunction call

8-15($t0-$t7): Temporary variables, sub-functions do not need to be saved and restored when used

16-23($s0-$s7): Subfunction register variable. The child function must save and restore the used variables before the function returns, so that the calling function knows that the values ​​of these registers have not changed.

24-25 ($t8-$t9): Temporary variables, sub-functions do not need to be saved and restored

26-27 ($k0-$k1): Usually used by interrupts or exception handlers to save some system parameters

28($gp): Global pointer. Some runtime systems maintain this pointer to more easily access the "static" and "extern" variables.

29($sp): stack pointer

30 ($s8/$fp): The 9th register variable. Subfunctions can be used to make pointers

31($ra): the return of the subfunction

Cp0: coprocessor 0, MIPS control of the CPU is completed with cp0