Design principle of SCA architecture based on ZedBoard

Abstract : ZedBoard is Xilinx's first fully programmable system-on-chip that combines ARM Cortex A9 dual-core and 7-series FPGAs. It combines the advantages of both ARM and FPGA and is one of the best embedded platforms for miniaturized SCA implementation. This paper introduces the hardware structure of the ZedBoard platform, and solves the problem that the SCA architecture cannot be implemented on the dedicated hardware platform. By analyzing the MHAL hardware abstraction layer technology and the OCP interface specification, the MHAL hardware abstract interface and FPGA conforming to the ZedBoard platform hardware environment are designed. The waveform component container effectively solves the implementation problem of the SCA architecture on the ZedBoard platform, and lays a foundation for implementing the SCA architecture-based system development on the ZedBoard.

Software CommunicaTIons Architecure (SCA) is the software radio implementation framework proposed by the US military in the Joint TaTIcal Radio System (JTRS) for the GPP environment. The JCAS is followed by the SCA supplemental standard to tailor the SCA architecture. The miniaturized SCA architecture can be built on the embedded hardware platform with limited hardware resources to enhance the reusability and portability of the system software. It is one of the main architectures for implementing the embedded reconfigurable system. ZedBoard is Xilinx's first embedded development environment that combines GPP and FPGA to meet the needs of most embedded system development. It is an inevitable development trend of embedded development environment, but because the application components in FPGA are all specific The implementation of the logic circuit is completely different from the program call execution on the GPP, so the SCA architecture has many implementation problems on the ZedBoard platform [1].

This paper first introduces the hardware structure of the ZedBoard platform, proposes the overall design of the SCA architecture based on ZedBoard, and focuses on the problems that the SCA architecture is difficult to implement on the ZedBoard platform. Through in-depth analysis of the Modem Hardware AbstraTIon Layer (MHAL) The standard and Open Core Protocol (OCP) interface protocol, combined with the ZedBoard hardware structure, designed the external abstract interface of the MHAL hardware platform and the SCA waveform component container, effectively solving the implementation problem of the SCA architecture on the ZedBoard, and implementing the SCA architecture on the ZedBoard. It laid the foundation for core system development.

The ZedBoard platform is Xilinx's first fully programmable system-on-chip that combines the ARM Cortex A9 dual-core and FPGA, combining the features and benefits of GPP and FPGA. The core of the ZedBoard platform is Xilinx's Zynq-7020 chip, which mainly includes processing system (PS) and programmable logic (PL). The PS part includes a dual-core ARM Cortex A9 processor, which is responsible not only for the management and configuration of the entire ZedBoard development board, but also as a stand-alone chip. It is the system control core of the ZedBoard platform, and also integrates the SIMD multimedia processing engine (NEON). ), memory controller (MMU) and other functional modules and a variety of external expansion interfaces, with a strong functional expansion capabilities. The PL part mainly includes Xilinx's high-performance 7 series FPGAs, which complements the PS part and provides rich IO resources and high-speed digital processing capabilities [2-3].

The overall design of the SCA architecture based on ZedBoard is shown in Figure 1. In order to give full play to the high-performance system control capability of the PS part of the ZedBoard platform, the core framework, middleware and operating system of the SCA architecture are designed to be implemented on the ARM part of the PS part; Part of the high-speed digital processing and reconfigurability features are ideal for implementing SCA application layer waveform components. In this paper, the self-designed MHAL hardware abstract interface and OCP waveform component container are used to solve the implementation problem of SCA architecture on FPGA, and the APC interface and IO bus of ZedBoard platform are used to realize the message transmission between the core framework of PS part and FPGA waveform component. The following focuses on the MHAL hardware abstraction interface and the FPGA waveform component container.

The Modem hardware abstraction layer MHAL is an interface standard promulgated by the JTRS office in 2007. Its original intention is to provide standard protocols and interfaces for communication between different processing units in the SCA system, and also to abstract the external interface of the hardware platform to implement SCA messages. The standard transmission on the ZedBoard provides a method [4-5]. This paper deeply analyzes and studies the MHAL standard, and combines the ZedBoard development environment to modify the MHAL message structure, redefines the functional structure and interface function of the MHAL hardware abstract interface, and designs the MHAL message sending and receiving structure of ARM and FPGA respectively. Completed the design of the MHAL hardware abstraction interface.

2.1 MHAL message structure design MHAL message is arranged from the least significant bit to the most significant bit in the form of address increment. In this paper, the message structure in the MHAL standard is modified and expanded, and the message start character and message type field are added to make it It can better meet the implementation requirements of the SCA architecture on the ZedBoard. The message structure is shown in Figure 2. The other fields are the same as the message structure in the MHAL standard, and will not be described here.