Isolated drive IGBT power device design skills eight questions

Power devices such as IGBTs, Power MOSFETs, and Bipolar Power Transistors need to be adequately protected against undervoltage, Miller effects, missing saturation, overload, and short-circuit damage. This article discusses the techniques for isolating power devices such as IGBTs through the eight questions and answers that Avago participated in.

1. How to avoid the Miller effect?

One of the problems faced by IGBT operation is the parasitic capacitance of the Miller effect. This effect is evident in the 0 to 15V type of gate driver (single power driver). The gate set-electrode coupling is due to the fact that high dV/dt transients can induce parasitic IGBT pass (gate voltage spikes) during IGBT turn-off, which is a potential hazard.

When the IGBT of the upper half bridge is turned on, the dVCE/dt voltage change occurs across the IGBT of the lower half bridge. Current will flow through Miller's parasitic capacitance, gate resistance and internal gate drive resistance. This will fall to the generation of the gate resistance voltage. If this voltage exceeds the IGBT gate threshold voltage, it may cause parasitic IGBT pass.

There are two traditional solutions. The first is to add the capacitance between the gate and emitter. The second solution is to use a negative gate drive. The first solution will result in a loss of efficiency. The extra cost required for the second solution is the negative supply voltage.

The solution is by shortening the gate-emitter path by using an additional transistor between the gate-emitter. After reaching a certain threshold, the transistor will short-circuit the gate-emitter region. This technology is called Active Miller Clamp and is available in our ACPL-3xxJ products. You can refer to the Avago application note AN5314

2. What are the fault protection functions? Are they integrated in the isolated drive?

Three fault protection functions are integrated into Avago's highly integrated gate driver ACPL-33xJ - UVLO (to avoid turning on the IGBT when VCC2 is not sufficient), DESAT (to protect IGBT overcurrent or short circuit), and Miller clamp (to prevent false triggering of IGBT caused by parasitic Miller capacitance)

3. In which applications should you consider the impact of the Miller effect?

One of the problems faced by IGBT operation is the parasitic capacitance of the Miller effect. This effect is evident in the 0 to 15V type of gate driver (single power driver). The gate set-electrode coupling is due to the fact that high dV/dt transients can induce parasitic IGBT pass (gate voltage spikes) during IGBT turn-off, which is a potential hazard.

When the IGBT of the upper half bridge is turned on, the dVCE/dt voltage change occurs across the IGBT of the lower half bridge. Current will flow through Miller's parasitic capacitance, gate resistance and internal gate drive resistance. This will fall to the generation of the gate resistance voltage. If this voltage exceeds the IGBT gate threshold voltage, it may cause parasitic IGBT pass.

There are two traditional solutions. The first is to add the capacitance between the gate and emitter. The second solution is to use a negative gate drive. The first solution will result in a loss of efficiency. The extra cost required for the second solution is the negative supply voltage.

The solution is by shortening the gate-emitter path by using an additional transistor between the gate-emitter. After reaching a certain threshold, the transistor will short-circuit the gate-emitter region. This technology is called Active Miller Clamp and is available in our door for the ACPL-3xxJ product.